1. Field of the Invention
The present invention relates to a video signal processor, and more particularly, to a synchronization detector of a video signal processor and a synchronization selector including the synchronization detector.
2. Description of the Related Art
Display systems including an optical disk player such as a digital versatile disk (DVD) player, a video cassette recorder, a TV system and a personal computer commonly include an apparatus for processing an input analog video signal.
An image displayed on a display system is comprised of a plurality of frames. In an interlaced scan method, a single frame includes two fields, that is, an odd field (or top field) and an even field (or bottom field) and each, single, field consists of a plurality of scan lines (or lines). A vertical synchronization signal VSYNC contains timing information for a field and corresponds to a single field and a horizontal synchronization signal contains timing information for a scan line and corresponds to a single scan line.
FIG. 1 is a block diagram of a conventional video signal processor 10. Referring to FIG. 1, the video signal processor 10 includes a Y/C separator 12, a synchronization detector 14 and a demodulator 16. The synchronization detector 14 detects a synchronization signal SYNC including a horizontal synchronization signal and a vertical synchronization signal that respectively define a horizontal scan period and a vertical scan period from an input analog video signal IVS.
The input analog video signal IVS can be a composite video blanking synchronization (CVBS) signal, a separate video signal or a component signal. The CVBS can be received through a tuner (not shown) of a video signal processor such as a television (TV) system. The separate video signal includes a luminance signal Y and a chrominance signal C and is input to a video signal processor such as a video cassette recorder. The component signal includes Y/Cb/Cr signals and is input to a video signal processor such as a DVD player.
The Y/C separator 12 separates (or extracts) the luminance signal Y and the chrominance signal C from the input analog video signal IVS based on the synchronization signal SYNC detected by the synchronization detector 14 when the input analog video signal IVS is a CVBS signal. When the input analog video signal IVS is a separate video signal or a component signal, however, the input video signal IVS is directly input to the demodulator 16 without being separated into the luminance signal Y and the chrominance signal C because the separate video signal or the component signal has already been separated into the luminance signal Y and the chrominance signal C.
The demodulator 16 interpolates the luminance signal Y and the chrominance signal C and generates a color signal suitable for the standard of a display device such as a liquid crystal display (LCD). That is, the demodulator 16 generates red, green and blue signals or a color signal in the form of a luminance signal Y and chrominance signals Cb and Cr according to the standard of the display device. The display device displays an image corresponding to the color signal generated by the demodulator 16 so that a user can see the image.
FIG. 2 illustrates a CVBS signal 20 corresponding to the input analog video signal IVS of FIG. 1. Referring to FIG. 2, the CVBS signal 20 includes a plurality of sections each having a front porch signal 21, a horizontal synchronization pulse 22, a back porch signal 23 including a color burst signal 24, and an active video signal 25. The waveform of the CVBS signal 20 having 525 lines corresponding to the NTSC (National Television System Committee) method is illustrated in FIG. 10.
Each of scan lines of the CVBS signal 20 is initiated at the falling edge FE of the horizontal synchronization pulse 22 and ends at the falling edge of the next horizontal synchronization pulse 22. The front porch signal 21 and the back porch signal 23 has a DC voltage referred to as a blank level BL (0V, for example). The horizontal synchronization pulse 22 has a DC voltage referred to as a synchronization level SL. The falling edge FE and the rising edge RE of the horizontal synchronization pulse 22 are determined based on a DC threshold level TL. For example, the falling edge FE and the rising edge RE of the horizontal synchronization pulse 22 can be set to 50% of the amplitude of the horizontal synchronization pulse 22. The amplitude of the horizontal synchronization pulse 22 corresponds to the absolute value of a difference between the blank level BL and the synchronization level SL.
A method of detecting a horizontal synchronization signal and a vertical synchronization signal from the CVBS signal 20 using the synchronization detector 14 will now be explained.
The blank level BL and the synchronization level SL are detected and a threshold level TL is determined using the detected blank level BL and the synchronization level SL. The falling edges FE or the rising edges RE of the horizontal synchronization pulses 22 are detected based on the determined threshold level TL. The horizontal synchronization signal including position information (that is, timing information) of the horizontal synchronization pulses 22 is detected using a difference between the detected falling edges FE or a difference between the detected rising edges RE. The vertical synchronization signal can be detected by counting the detected horizontal synchronization signal by half the number of lines of the CVBS signal 20.
However, the method of detecting the horizontal synchronization signal and the vertical synchronization signal cannot detect horizontal and vertical synchronization signals correctly when the blank level BL and the synchronization level SL become varied due to noise or when the falling edges FE or the rising edges RE of the horizontal synchronization pulses 22 become distorted (or damaged) due to noise.